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Chipz
Validation Tools
Synthesis
Testbench (soon)
Changes:
Review
Automatic
SDD Options
Compilation
Synthesis
🚀
Choose Your Mode
Select how you'd like to work with Chipz AI
🎯
Vibe Mode
General RTL development chat with code generation
• Natural language to Verilog conversion
• Interactive code refinement
• Validation tools integration
📋
Spec-Driven Development
Process documentation URLs and extract structured design elements
• Documentation URL processing
• Structured element extraction
• Organized specification generation
✅
Verification Mode
Generate a structured verification plan from your existing specs
• Requirement extraction and normalization
• Test and coverage planning
• Assertion and checker proposals
Start a conversation
Describe the Verilog module you want to create
SDD Mode Active
Paste a documentation URL to extract structured design elements
Supported sites:
• OpenTitan: docs.opentitan.org
• ReadTheDocs: *.readthedocs.io
• GitHub Pages: *.github.io
Verification Mode Active
Generate a verification plan from your existing spec or micro-architecture
Example prompts:
• "Generate verification plan from my spec"
• "Create a vplan for specs/spec_uart.md"
• "Extract requirements and build a verification plan"
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Vibe
SDD
Verify